The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, in FINFET fabrication processes, it is typical to epitaxially grow some semiconductor materials over semiconductor fins as S/D features, referred to as EPI S/D features. Many technical efforts have been directed to the engineering of the size, shape, and material of these EPI S/D features. But, issues remain. One issue is related to spacing between EPI S/D features. When the spacing is large, cavities might be introduced at the bottom of an S/D contact that straddles over multiple EPI S/D features. This is caused by excessive etching into a dielectric material surrounding the EPI S/D features during the contact formation process. Another issue is related to the size of EPI S/D features. Large EPI S/D features typically increase the circuit's parasitic capacitance associated with source and drain terminals. Also, large EPI S/D features are more prone to patterning damages during S/D contact formation process. On the other hand, having small EPI S/D features typically increases the spacing among them, which might suffer the cavity issue discussed above.
Accordingly, improvements in the FINFET EPI S/D engineering are desirable.